1. Field of the Invention
This invention relates generally to analog to digital converter circuits and, more particularly, to dual slope analog to digital converter circuits. The present invention provides for improved resolution in the conversion process and provides for reduced sensitivity of the conversion process to certain circuit parameters, such as changes in the supply voltage.
2. Description of the Related Art
Referring to FIG. 1, an illustration of one technique for the conversion of an analog input signal to a digital output signal. An input voltage V.sub.IN =V.sub.1 is applied to the input terminal of an integrator circuit. The charging of the capacitor associated with the integrator circuit provides a linear output voltage VOUT with a slope generally proportional to the magnitude of the input voltage. Thus V.sub.3 &gt;V.sub.2 &gt;V.sub.1 as illustrated in FIG. 1. After a time T.sub.0, the input voltage is replaced by a zero voltage signal, i.e., V.sub.IN =0, the capacitor in the integrating circuit will discharge at a rate determined by the circuit parameters. Thus, the charge on the integrator circuit capacitor resulting from application of V.sub.IN =V.sub.1 for a period T.sub.0 will be removed in a time T.sub.1, the charge on the integrator circuit capacitor resulting from application of V.sub.IN =V.sub.2 for a period of T.sub.0 will be removed in a time T.sub.2 and the charge on the integrator circuit capacitor resulting from the application of V.sub.IN =V.sub.3 will be removed in a time T.sub.3. The quantities T.sub.1, T.sub.2 and T.sub.3 or T.sub.0 +T.sub.1, T.sub.0 +T.sub.2 and T.sub.0 +T.sub.3 define, except for an additive and/or a multiplicative scaling factor, the voltage levels of V.sub.1, V.sub.2 and V.sub.3, respectively.
Referring to FIG. 2, a block diagram of the apparatus for performing the dual slope analog to digital conversion of the prior art is illustrated. The timer unit 24 causes the voltage V.sub.IN to be applied to the integrator circuit 21 (the integrator circuit including capacitor C and resistor R). The voltage at the output terminal of integrator circuit 21 begins to fall and causes comparator 23 to change states when V.sub.OUT falls below V.sub.COMP. After a preestablished time, T.sub.0, the timer unit 24 causes the ground or common potential to be applied to integrator circuit 21 and the voltage V.sub.OUT begins to rise. When the V.sub.OUT rises above V.sub.COMP, the output voltage V.sub.OUT (23) of comparator 23 changes state and stores the time which has elapsed since the switch unit 22 initiated the timing procedure. As indicated in FIG. 1, the voltage V.sub.OUT (23) will be delayed (generally referred to a hysteresis) until the V.sub.OUT is approximately equal V.sub.COMP.
The prior art involving dual slope analog to digital converter circuits is extensive. U.S. Pat. No. 3,978,471 by Kelly describes a digital thermometer that uses a low precision voltage source and temperature dependent resistive element to provide a temperature dependent voltage for a dual slope analog to digital converter. The variations in the voltage source are compensated for by a plurality of switches that select the voltage to be applied to the analog to digital converter. U.S. Pat. No. 4,364,028 by Masuda et al describes the use of a control circuit to select a correction voltage to a second terminal of an operational amplifier to compensate for the (internally generated) offset voltage. The control circuit selects a position of resistance dividing network to provide the appropriate correction voltage. U.S. Pat. No. 4,379,260 by Labus describes a technique for compensating for instabilities in an analog to digital converter circuit by storing a charge related to the instability on a capacitor and using the stored charge to compensate for the instability. The compensation technique requires a plurality of switches activated at the appropriate time to compensate for the instability. U.S. Pat. No. 4,445,111 by Swift et al describes a dual slope analog to digital converter circuit that uses an accurate reference source and inaccurate reference source. Apparatus is described for comparing the accurate and the inaccurate reference sources and providing a factor for the correction of the inaccurate reference source. U.S. Pat. No. 4,485,372 by Holloway describes apparatus for improving the accuracy of an analog to digital converter circuit by using a first stage including successive approximation apparatus to develop the higher order digital bits and a second stage using a dual slope analog to digital converter to provide the lower order digital bits. Another technique for improving the accuracy of an analog to digital conversion is described by U.S. Pat. No. 4,558,303 by Fielden wherein a first approximation to the digital designation is made by comparison of the input voltage to a series of voltages determined by a precision resistance dividing network and a reference voltage. The values between those provided by the resistance dividing network are determined by a comparison of the input voltage with a ramp voltage generated between the nearest two values of the resistance dividing network. In U.S. Pat. No. 4,596,977, an "out of range" voltage for a dual slope analog to digital converter circuit is detected by a timer which determines that the time for the integration of the input signal, that was anticipated for the selected range, has been exceeded. In U.S. Pat. No. 4,617,550 by Glineman, a dual slope analog to digital converter circuit is described that, when the integration is to exceed a predetermined level (beyond which the circuit components can not operate as desired), a reference voltage of opposite polarity is applied to the integrating portion of the converter circuit to discharge the capacitor a known amount, thereby permitting the converter circuit to provide digital designations for signals that would otherwise be too large to measure. In U.S. Pat. No. 4,633,221 by Bradshaw et al, a technique for providing a plurality of ranges for a dual slope analog to digital converter is described. The technique relies on precision components and charges the capacitor for a known period of time. The capacitor discharges and a measurement is taken. When the measurement of the discharge time is less than a predetermined time, the charging time is increased. The process is repeated until a sufficiently large count indicates that the appropriate range has been reached. In U.S. Pat. No. 4,644,323 by Chamran, another technique for providing a dynamic range adjustment for an unknown input signal for a dual slope analog to digital converter is described. Using this technique, when a input signal causes the integrated charge to exceed a predetermined value in a given period of time, the time period for integration caused by the input signal is shortened by a given amount until the capacitor charge remains less than the predetermined value. A known reference voltage is used to discharge the capacitor and the charging and discharging time are compared to obtain a digital value. U.S. Pat. No. 4,661,803 by Nishiyama describes a technique for compensating for changes in the supply voltage by an initialization procedure in which a charge, related to the supply voltage, is stored on a capacitor prior to the determination of a digital value for an input voltage. The stored charge provides compensation, during the measurement period for changes in the supply voltage.
Therefore, in the prior art, apparatus has been disclosed which can improve the accuracy of the analog to digital converter circuit for both fluctuations in supply voltage and range selection. The apparatus typically involves precision components and/or additional switching apparatus usually involving additional control circuits. A need has therefore been felt for apparatus and an associated method that can compensate for fluctuations in supply voltage and can minimize the requirement for precision components while still providing for a plurality of measurement ranges for input voltages.